Types of Interrupts

The 8085 microprocessor supports two types of interrupts:

• Hardware Interrupts: Generated by external devices through dedicated pins on the CPU. 8085 has 5 hardware interrupts: i.e. TRAP, RST7.5, RST6.5, RST5.5, INTA.

• Software Interrupts: Generated by the program itself using specific instructions (RST 0 to RST 7). Used for internal tasks like system calls.

Non-Vectored Interrupts:

• In a non-vectored interrupt system, when an interrupt occurs, the processor transfers control to a fixed memory location where the interrupt service routine (ISR) starts.
• The ISR must determine the source of the interrupt by checking status flags or polling external devices to identify which device generated the interrupt.
• This method is simpler and requires less hardware support but may lead to longer interrupt response times since the ISR needs to identify the interrupt source.

Vectored Interrupts:

• In a vectored interrupt system, when an interrupt occurs, the processor automatically determines the location of the ISR by using a unique vector address associated with each interrupt source.
• The vector address is typically stored in a vector table located in a specific memory location.

For Hardware interrupts vector addresses are given by:

INTERRUPT	VECTOR ADDRESS
TRAP (RST 4.5)	24 H
RST 5.5	2C H
RST 6.5	34 H
RST 7.5	3C H

For Software interrupts vector addresses are given by:

INTERRUPT	VECTOR ADDRESS
RST 0	00 H
RST 1	08 H
RST 2	10 H
RST 3	18 H
RST 4	20 H
RST 5	28 H
RST 6	30 H
RST 7	38 H

• This method requires additional hardware to manage the vector table, but it offers improved efficiency and faster interrupt handling.

Maskable Interrupts:

• Maskable interrupts are those interrupts that can be temporarily disabled or masked by the processor, preventing their immediate processing.
• Examples of maskable interrupts include external hardware interrupts, timer interrupts, and I/O interrupts.
• For example: RST7.5, RST6.5, RST5.5.

Non-Maskable Interrupts (NMI):

• Non-maskable interrupts are interrupts that cannot be disabled or masked by the processor.
• When a non-maskable interrupt occurs, the processor immediately suspends the execution of the current instruction and transfers control to the corresponding interrupt service routine (ISR).
• Non-maskable interrupts are essential for handling critical events such as power failure, system reset, hardware malfunctions, or other emergencies.
• For example: TRAP.